发明名称 |
Integrated circuit that processes communication packets with scheduler circuitry that executes scheduling algorithms based on cached scheduling parameters |
摘要 |
An integrated circuit processes a communication packet and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packet. The scheduling circuitry retrieves first scheduling parameters cached in a context buffer for the packet and executes a first algorithm based on the first scheduling parameters to schedule subsequent transmission of the communication packet.
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申请公布号 |
US6888830(B1) |
申请公布日期 |
2005.05.03 |
申请号 |
US20000639915 |
申请日期 |
2000.08.16 |
申请人 |
MINDSPEED TECHNOLOGIES, INC. |
发明人 |
SNYDER II WILSON P.;TOMPKINS JOSEPH B.;LUSSIER DANIEL J. |
分类号 |
G06F9/30;G06F9/38;H04L12/56;H04Q11/04;(IPC1-7):H04L12/56;G06F3/00 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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