| 摘要 |
<p>The invention concerns a design analysis technique for a test pattern analysis of chips via an automatic test equipment (ATE) or a circuit simulation to detect potential design weakness or unnormal behavior in real customer application faults. One object of the invention is to prevent the disadvantage of the prior art to provide an analysis technique to localize the design weakness or faults due to application failures, to provide an analysis technique which actually shows when the chip fails and how it fails and to provide an analysis technique for a much longer test sequence. <??>The problems are solved by comprising a simulation procedure stored in a LRT database of a automatic test equipment (ATE), defining test conditions and test patterns which executes and generates continuously for a time given by a user, applying the test stimuli and test conditions to a device under test (DUT) and starting the long running test (LRT), stop the test automatically if any application faults occurs and log the failure time and timely test sequence and starting another test again until a given maximum number of test is reached. <IMAGE></p> |
