发明名称 |
ACCELERATED LIFE TEST OF MRAM CELLS |
摘要 |
A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.
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申请公布号 |
US2005068815(A1) |
申请公布日期 |
2005.03.31 |
申请号 |
US20030672959 |
申请日期 |
2003.09.26 |
申请人 |
GARNI BRADLEY J.;ANDRE THOMAS W.;NAHAS JOSEPH J. |
发明人 |
GARNI BRADLEY J.;ANDRE THOMAS W.;NAHAS JOSEPH J. |
分类号 |
G11C11/15;G11C29/50;(IPC1-7):G11C7/00;G11C29/00 |
主分类号 |
G11C11/15 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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