| 摘要 |
PROBLEM TO BE SOLVED: To provide a header receiving circuit which can realize a speed enhancement of a decoding processing by enhancing an interpretation speed of a header portion. SOLUTION: A header receiving circuit includes a data counter 14a, a marker detection circuit 14b, and a specified marker data skip means 14 which controls a data output stop signal outputted to a second address counter 13 and a subsequent data request signal outputted to an external memory 1, and which skips reading of data of the specified marker received from the external memory 1 on the basis of a detection result of a specified marker such as APP and COM by the marker detection circuit 14b, a count of the data counter 14a to which a data amount of the marker is set, and a memory capacity of a FIFO buffer memory 12. COPYRIGHT: (C)2005,JPO&NCIPI |
