SEMICONDUCTOR INTEGRATED CIRCUIT FOR PERFORMING ERASE OPERATION AT HIGH SPEED WITHOUT ANY DEPLETION HALFWAY THROUGH ERASE OPERATION

摘要

PURPOSE: A semiconductor integrated circuit is provided to perform the erase operation of a memory cell at high speed without any depletion halfway through the erase operation despite the shutdown of the operating power source by successively performing the first write process of the nonvolatile memory cells that may exceed the depletion level in the erase process. CONSTITUTION: A semiconductor integrated circuit comprises nonvolatile memory cells having a threshold voltage which is changeable reversibly by electrical erasing and writing; a control circuit for controlling the change of the threshold voltage of the nonvolatile memory cell. Wherein the control circuit controls an erase process for simultaneous erasing of one unit memory cell among plural nonvolatile memory cells, the first write process for writing onto a specific unit memory cell when a limit of a threshold voltage distribution is exceeding the first level, and the second write process for writing onto a specific unit memory cell when the limit of the threshold voltage distribution is exceeding the second level after the first write process is completed. And the erase process is that the repetition of an erase verification(S2) for determining whether the limit of the threshold voltage distribution in a counter-erase direction reaches the erase determination level, and an application of the erase voltage.