发明名称 |
Multi-processor system including a mode switching controller |
摘要 |
Any of the processors CPU1 to CPUn turns the miss hit detecting signal line 5 to a low level upon detecting occurrence of a miss hit. In response, the mode switching controller 2 is notified of the occurrence of a miss hit and switches each of the processors CPU1 to CPUn to the synchronous operation mode. Also, each command from each of the processors CPU1 to CPUn is appended with a tag. When each of the processors CPU1 to CPUn feeds the synchronization detecting signal line 6 with the tags which are identical as designated as a synchronous point, the operation of the processors can be switched to the non-synchronous operation mode by the mode switching controller 2.
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申请公布号 |
US6857052(B2) |
申请公布日期 |
2005.02.15 |
申请号 |
US20020078533 |
申请日期 |
2002.02.21 |
申请人 |
SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER |
发明人 |
AMANO HIDEHARU |
分类号 |
G06F12/08;G06F9/45;G06F9/46;G06F9/52;G06F9/54;G06F12/00;G06F15/16;G06F15/167;G06F15/177;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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