发明名称 Pipeline control for power management
摘要 A method and apparatus for managing power consumption in logic modules without causing power surges. A first and second logic module operate in response to a first and second clock signal, respectively, to carry out a command. When the command arrives, the first logic module begins to operate and indicates that it is busy. After a first delay, the second module begins to operate and indicates that it is busy. When both modules are finished and no new command is available, the busy indicators are deactivated and after a second delay the first clock signal is deactivated. A third delay after the first clock signal is deactivated, the second clock is deactivated. The first, second and third delays are programmable to avoid power surges in the respective modules.
申请公布号 US6853929(B2) 申请公布日期 2005.02.08
申请号 US20030428392 申请日期 2003.05.01
申请人 VIA TECHNOLOGIES, INC. 发明人 WENG KUOYIN;HUANG HSILIN;CHENG CHIENKANG
分类号 G05B11/00;G06F1/32;G06F19/00;H01L27/00;H03K5/13;H03K19/00;(IPC1-7):G06F19/00 主分类号 G05B11/00
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