| 摘要 |
PROBLEM TO BE SOLVED: To provide a method of forming a metal wiring in a semiconductor element restrained from creating a fence generated in the periphery of a via hole in a dual damascene structure. SOLUTION: After forming interlayer insulation layers 405, 407, a hard mask layer made of an antireflection film and a resist layer on a semiconductor substrate 400, a first pattern for defining a via hole is formed, and the hard mask layer and interlayer insulation layers are etched through the use of the first pattern as a mask to form a partial via hole 412. Next, after eliminating the residual resist, a resist layer is formed on the overall surface and while still leaving the resist within the partial via hole 412 over, a second pattern 416 for defining a trench wiring region 418 that partially overlaps the partial via hole 412 is formed. After forming a hard mask pattern 408b using the second pattern 416 as a mask, the residual resist is eliminated, and the interlayer insulation layers 405, 407 are etched using the hard mask pattern as a mask to form the trench wiring region 418 and a full via hole that is an extension of the partial via hole 412. COPYRIGHT: (C)2005,JPO&NCIPI
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