Circuit arrangement to generate a clock signal for a sigma-delta analog-to-digital converter

摘要

The method involves determining a variable periodic duration (T,T*) of the power supply network (PL) in time units of a system clock signal (C) and generating a sampling clock signal (S) by distributing a constant number of pulses over the determined periodic duration so that the frequency of the sampling clock signal is an integral multiple of the frequency of the power supply network. The number of pulses equals the decimation rate of the analog-to-digital converter (20). An independent claim is also included for the following: (a) an arrangement for implementing the inventive method.