发明名称 Semiconductor memory device with reduced power consumption
摘要 In a semiconductor memory device having a shared sense amplifier configuration, a control circuit outputting a bit line isolation signal latches a block selection signal in accordance with a change in a trigger signal. With this configuration, when the same block is selected, no change is caused in the bit line isolation signal. Consequently, charge/discharge current is reduced, and power consumption is reduced. Since a specific bit in a refresh counter is not used, unlike the conventional technique, the design changes little even in the case of changing the configuration of an array.
申请公布号 US6845056(B2) 申请公布日期 2005.01.18
申请号 US20020325827 申请日期 2002.12.23
申请人 RENESAS TECHNOLOGY CORP. 发明人 KINOSHITA MITSUYA
分类号 G11C11/407;G11C8/08;G11C8/12;G11C11/406;G11C11/408;G11C11/409;G11C11/4091;(IPC1-7):G11C8/00 主分类号 G11C11/407
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