发明名称 Inductance and via forming in a monolithic circuit
摘要 A method for manufacturing, in a monolithic circuit including a substrate, an inductance and a through via, including the step of forming, from a first surface of the substrate, at least one trench according to the contour of the inductance to be formed; forming by laser in the substrate a through hole at the location desired for the via; simultaneously insulating the surface of the trench and of the hole; and depositing a conductive material in the trench and at least on the hole walls.
申请公布号 US6830970(B2) 申请公布日期 2004.12.14
申请号 US20020268370 申请日期 2002.10.10
申请人 STMICROELECTRONICS, S.A. 发明人 GARDES PASCAL
分类号 H01L27/02;H01F17/00;H01F41/04;H01L21/02;H01L21/768;(IPC1-7):H01L29/00;H01L21/823 主分类号 H01L27/02
代理机构 代理人
主权项
地址
您可能感兴趣的专利