| 摘要 |
A clock-signal generator-converter device has a first phase locked loop (PLL1) for obtaining a first clock signal (TS1) from one of several data signals (DS1) having different data signalling rates, in which a data signal is supplied to the first phase locked loop (PLL1) as a reference signal (fR1). A second phase locked loop (PLL2) converts the first clock signal (TS1 into an associated second clock-signal (TS2) having a different clock frequency. The first clock-signal is supplied as a second reference signal (fR2) via a frequency divider (FT4), connected on the input side, to the second phase locked loop (PLL2), in the feedback path of which is connected a second adjustable frequency divider (FT2) for roughly adapting to the different rates of the data signals (DS1) and a third frequency divider (FT3,FT5) for generating the second clock signal (TS2) at another clock frequency. |
