发明名称 Sample-and-hold with no-delay reset
摘要 An integrated circuit having a sample-and-hold device is provided, which can be operated in successive cycles which each include a sample phase and a hold phase. During a sample phase a first storage device is charged to a voltage value proportional to an analog input signal, which voltage value is provided for a further circuit part of the integrated circuit in the hold phase. A second storage device is charged during a first cycle to a voltage value which is inverted relative to a final voltage value of the first storage device in the hold phase. In the sample phase of the next cycle following the first cycle, the second storage device is connected to the first storage device in order to discharge the first storage device.
申请公布号 US2004239378(A1) 申请公布日期 2004.12.02
申请号 US20040889377 申请日期 2004.07.12
申请人 BOGNER PETER 发明人 BOGNER PETER
分类号 G11C27/02;(IPC1-7):H03K5/00 主分类号 G11C27/02
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