Flexible deactivation of row memory lines in dynamic memory components, especially RLDRAM components, whereby a device is used to selectively delay deactivation of a memory row address

摘要

Dynamic memory component or RLDRAM (reduced latency DRAM) component in which deactivation of a row address during repeated access to a memory bank in the RLDRAM component can be delayed via a device, or address decoder, for flexible deactivation of address rows. Delayed deactivation occurs when an access row address remains unchanged compared with the previous memory access row address. An independent claim is made for a method for flexible activation and deactivation of a row address in an RLDRAM.