发明名称 |
METHOD FOR AUTOMATICALLY DETERMINING FLOOR PLAN |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for automatically determining a floor plan that makes it possible to reduce the time to process a floor plan by reducing the number of times that the floor plan is remade. SOLUTION: The method for automatically determining the floor plan of a semiconductor integrated circuit comprises an extraction step for extracting a register F and logic operation cells W-Z; a cluster generation step for generating an assembly of the logic operation cells W-Z as a cluster cell; a first cell positioning step for determining the positions of the cluster cell and the register F in such a way that the logic operation cells W-Z within the cluster cell are located in proximity to one another; a selection step for selecting logic hierarchy blocks that determine the floor plan; and a hierarchy block positioning and wiring area determining step for determining an area where the logic hierarchy blocks are positioned. COPYRIGHT: (C)2005,JPO&NCIPI
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申请公布号 |
JP2004334565(A) |
申请公布日期 |
2004.11.25 |
申请号 |
JP20030130157 |
申请日期 |
2003.05.08 |
申请人 |
RENESAS TECHNOLOGY CORP |
发明人 |
SAITO TAKESHI;INOUE YOSHIO;KAIMOTO KOJI |
分类号 |
G06F17/50;G11C11/00;H01L21/82;H01L27/02;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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主权项 |
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地址 |
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