AMPLIFICATION CIRCUIT HAVING OUTPUT DELAY TIME CHANGED SELECTIVELY ACCORDING TO COMMON MODE VOLTAGE LEVEL, REPLICA DELAY CIRCUIT INCLUDING THE SAME, AND INTERNAL CLOCK GENERATION CIRCUIT INCLUDING THE REPLICA DELAY CIRCUIT CAPABLE OF COMPENSATING FOR THE PHASE OFFSET OF INTERNAL CLOCK SIGNAL

摘要

PURPOSE: An amplification circuit having an output delay time changed selectively according to a common mode voltage level, a replica delay circuit including the same, and an internal clock generation circuit including a replica delay circuit are provided to compensate for a phase offset by delaying variously a phase of an internal clock signal. CONSTITUTION: An amplification circuit includes a first amplifier and a second amplifier. The first amplifier(101) is used for outputting internal signals in response to input signals and changing a common mode voltage level of the internal signals in response to control signals. The second amplifier(102) is used for comparing voltage levels of the internal signals, outputting an output signal according to a compared result, and changing a duty cycle of the output signal according to a change of the common mode voltage level of the internal signals.