| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a variable frequency divider capable of performing a more stable high-speed operation without increasing the bit width of a counter. <P>SOLUTION: N1 is loaded as an initial value on a binary down-counter 12 when a count value becomes -N2. Also, the most significant bit of the count value of the counter 12 is used as a frequency division control signal PCTR, and when the N1 is loaded, the signal PCTR reaches an L level and the signal PCTR reaches an H level when the count value becomes "-1". Since the number of frequency division of a DMPS 11 is directly controlled by the most significant bit of the count value, the delay of a switching operation in the DMPS 11 hardly occurs. Also, the most significant bit of the count value is outputted as a clock signal CLKOUT 2 to the outside. By setting N1 and N2 at values close to each other values, the bit width of the counter 12 can be made small and a duty ratio of the clock signal CLKOUT 2 can be close to a value of 50%. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
