| 摘要 |
PROBLEM TO BE SOLVED: To stabilize power fluctuation in DMA transfer. SOLUTION: A CPU 42 for totally controlling circuits of a digital camera is equipped with an instruction cache 42A for storing control instructions comprising a program and runs the program stored in an SDRAM 54. In a photography standby state before fully pressing a shutter button 20, image data of moving images in small data sizes are DMA-transferred from a signal processing circuit 36 to the SDRAM 54, and the moving images are indicated on a display in real time. After the shutter button 20 is fully pressed, image data of still pictures in large data sizes are DMA-transferred from the signal processing circuit 36 to the SDRAM 54, and the CPU 42 invalidates the instruction cache 42A to read and run the program from the SDRAM 54 at all the time. Thus, the frequency of access to the SDRAM 54 is improved and when starting the DMA transfer of the still pictures and during transfer, power fluctuation is suppressed. COPYRIGHT: (C)2005,JPO&NCIPI |
