| 摘要 |
The transmitter circuit architecture is disclosed based on a phase lock loop architecture and which uses a delta-sigma modulator with 2 point modulation. In order to restrict the bandwidth of the PLL, subsidiary analogue modulation is employed, which requires aligning with the delta-sigma modulation. Alignment of the modulation is accomplished by correction of the sensitivity of the PLL voltage controlled oscillator to modulation by correlating residual modulation in the PLL with the modulated signal input. The action of the modulation correlator trims the modulation and the PLL bandwidth without disturbing the normal operation of the transmitter, and allows the use of modulation bandwidths greater than the PLL bandwidth.
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