发明名称 |
Semiconductor integrated circuitry and method for manufacturing the circuitry |
摘要 |
A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.
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申请公布号 |
US6800888(B2) |
申请公布日期 |
2004.10.05 |
申请号 |
US20040759238 |
申请日期 |
2004.01.20 |
申请人 |
HITCHI, LTD.;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
WATANABE KOZO;OGISHIMA ATSUSHI;MONIWA MASAHIRO;HASHIMOTO SYUNICHI;KOJIMA MASAYUKI;OHYU KIYONORI;KURODA KENICHI;MATSUDA NOZOMU |
分类号 |
H01L21/8242;H01L27/105;H01L27/108;(IPC1-7):H01L29/76;H01L29/94;H01L31/062;H01L31/113;H01L31/119 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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