| 摘要 |
A method and an arrangement for testing digital circuits having at least one circuit logic and memory elements, which are interconnected to form at least one shift chain, in which test vectors are inserted into the shift chain and result vectors are retrieved from the shift chain. In at least one part of the shift chain, values from the memory elements are fed back to logic units, and the feedback values are combined with updated output values of the circuit logic in the logic units, and output values of the logic units are stored as internal test vectors in the memory elements in an internal test mode.
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