| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the delay time for subtraction in a block unit computing element and perform arithmetic operation while maintaining the operating frequency in a circuit for carrying out multiple length calculation of Montgomery multiplication residues. <P>SOLUTION: In a complement mode, an encoder means 202 of a secondary Booth algorithm outputs a selection signal different from that in a normal mode wherein the multiplication A×B is performed, and a selection means 203 selects a partial product representing -A for the three bits b<SB>1</SB>, b<SB>0</SB>, b<SB>-1</SB>of B and selects a partial product representing 0 for the other bits. An adding means 204 adds the partial product representing -A and 0, and outputs -A (two's complement number of A, or one's complement number of A). <P>COPYRIGHT: (C)2004,JPO&NCIPI |
