Phase locked loop (PLL) for frequency synthesis, i.e. generating signal with required frequency, with output signal of digitally energisable, voltage controlled oscillation (VCO) converted into allocated phase signal

摘要

PLL comprises digitally tunable VCO (1) with energising input (3) and output (2) for required frequency signal. To VCO output is coupled convertor (4) delivering digitally coded phase information (psi div), allocated to frequency of output signal (fvco).A substractor (5) has first input for reference phase (psi ref), and second input for digital coded phase information derived from frequency of output signal. Its output delivers phase difference (psi err) and is coupled to VCO tuning input. Converter is designed as flank counter.