发明名称 |
Process for forming dual metal gate structures |
摘要 |
A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.
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申请公布号 |
US6790719(B1) |
申请公布日期 |
2004.09.14 |
申请号 |
US20030410043 |
申请日期 |
2003.04.09 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
ADETUTU OLUBUNMI O.;LUCKOWSKI ERIC D.;SAMAVEDAM SRIKANTH B.;MARTINEZ, JR. ARTURO M. |
分类号 |
H01L21/8234;(IPC1-7):H01L21/337 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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