发明名称 Method of manufacturing semiconductor device having dual damascene structure
摘要 A via hole is formed to reach a Cu interconnection through an interlayer insulating film that covers the Cu interconnection. A conductive polymeric member is buried in the via hole electrolytically. A resist pattern is formed on the interlayer insulating film by photolithography, and a trench is formed, connected to the via hole, by etching, using the resist pattern as a mask. The resist pattern and the conductive polymeric member are removed thereafter.
申请公布号 US6787454(B1) 申请公布日期 2004.09.07
申请号 US20030683392 申请日期 2003.10.14
申请人 RENESAS TECHNOLOGY CORP. 发明人 SAITO TAKAYUKI
分类号 H01L21/768;(IPC1-7):H01L21/476 主分类号 H01L21/768
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