SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING DATA OUTPUT TIMING, IN WHICH OUTPUT TIMING OF ALL DATA IS EQUAL

摘要

PURPOSE: A synchronous semiconductor memory device capable of controlling data output timing is provided to improve fabrication product ratio by controlling data output timing in a burst read operation. CONSTITUTION: According to a data output control circuit(200), an output control circuit(250) outputs control signals(ZRDH0,ZRDL0) to set a level of a data signal(DQ) being output from a data output circuit(240). A delay control unit(210) outputs the control signal(ZRDH0) at one propagation time on the ground of the control signal from a signal propagation control circuit(230). The data output circuit has a P channel MOS transistor(242) and an N-channel MOS transistor(243) and an inverter(241). The signal propagation control circuit(230) has a NAND circuit(231), an inverter(232), a clock inverter(233) and a latch circuit(235).