发明名称 |
Method for reducing poly-depletion in dual gate CMOS fabrication process |
摘要 |
Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical principles. First, the doping efficiency is increased when the dose of N+ ion implantation is increased. Second, the doping efficiency is increased when the thickness of N+ polysilicon is reduced. Third, the increase of depletion caused by the reduction of the channel width is inhibited when the EFH is adjusted to be less than 0. Fourth, the overall doping efficiency is increased when each step of polysilicon deposition and ion implantation is divided into multiple steps.
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申请公布号 |
US2004166623(A1) |
申请公布日期 |
2004.08.26 |
申请号 |
US20030712921 |
申请日期 |
2003.11.13 |
申请人 |
LEE CHANG YEOL;CHOI DEUK SUNG |
发明人 |
LEE CHANG YEOL;CHOI DEUK SUNG |
分类号 |
H01L27/092;H01L21/28;H01L21/8228;H01L21/8238;(IPC1-7):H01L21/823;H01L21/320;H01L21/476 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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