发明名称 Parallel execution processor and instruction assigning method
摘要 The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unit 120 forms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor 100.
申请公布号 US2004133765(A1) 申请公布日期 2004.07.08
申请号 US20030686746 申请日期 2003.10.16
申请人 TANAKA TAKESHI;TAKASHIMA SATOSHI;NISHIDA HIDESHI;KIMURA KOZO;KIYOHARA TOKUZO 发明人 TANAKA TAKESHI;TAKASHIMA SATOSHI;NISHIDA HIDESHI;KIMURA KOZO;KIYOHARA TOKUZO
分类号 G06F9/30;G06F9/318;G06F9/38;(IPC1-7):G06F9/30 主分类号 G06F9/30
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