| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor circuit in which an ESD resistance is improved as a chip area remains suppressed. SOLUTION: NMOS transistors 14 and 15 diode-connected in the directions where the signal conductor 13 side is used as a cathode and the grounds GND1 and GND2 sides as anodes are formed among a signal conductor 13 and grounds GND1 and GND2 while PMOS transistors 16 and 17 diode-connected in the directions that the power supplies VDD1 and VDD2 sides are used as the cathodes and the signal conductor 13 side as the anode are formed among both power supplies VDD1 and VDD2 and the signal conductor 13. COPYRIGHT: (C)2004,JPO&NCIPI
|
