Semiconductor memory device including power generation circuit implementing stable operation

摘要

An array power generation circuit supplying an array power supply voltage to a corresponding memory array block and a peripheral power generation circuit supplying a peripheral power supply voltage to a peripheral circuit are arranged around each memory array block. Respective power supply voltages are generated under the same reference voltage level, and transmitted in an array power supply line and a peripheral power supply line. An N channel MOS transistor is connected between the array power supply line of the array power generation circuit and the peripheral power supply line of the peripheral power generation circuit. The N channel MOS transistor is turned on when the gate thereof receives a boosted voltage from a booster circuit, and electrically couples the array power supply line and the peripheral power supply line.