| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and its test method in which an increment of a gate scale required for a test of memory macro-cell can be suppressed to the minimum, a test can be performed with a high operation frequency and power consumption at the time of simultaneous test can be reduced. SOLUTION: A test is realized by only one data comparing part 6 for a plurality of memory macro-cells 4, 5 by connecting the plurality of memory macro-cells 4, 5 in series, also, when the plurality of memory macro-cells 4, 5 are connected in series, memory macro-cells 4, 5 being adjacent each other are connected. Thereby, length of a wiring from an output pin of read-data 27 of the memory macro-cell 4 of a preceding stage of the memory macro-cells connected each other to an input pin of write-data 32 of the memory macro-cell 5 of the poststage becomes short, and data delay quantity at the time of a test is reduced. COPYRIGHT: (C)2004,JPO
|
