| 摘要 |
A nonvolatile memory apparatus contains plural memories, at least one of which is a nonvolatile memory, and a processing unit. Data input/output (I/O) terminals of the memories and processing unit are mutually coupled by a bus. When the nonvolatile memory is brought into an erasing mode by the processing unit, it becomes electrically isolated as a result of freeing the connection of the I/O terminal thereof during the erase operation. Accordingly, the processing unit is capable of accessing other memories via the bus where information can then be transferred/received between other memory devices and, otherwise, with the input/output port of the system. Control by the processing unit requires a relatively short time during which the erasing commencement is instructed so as to minimize interruption of the throughput capability of the system. Following the designation of an erasing mode, a data polling mode is designated.
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