| 摘要 |
PROBLEM TO BE SOLVED: To improve a controller part and to optimize a memory size so as to improve simulation speed, in a conventional system, wherein an RTL model and an operation model are mixed, provided with an interface model for executing simulation with clock precision to match input and output of the operation model and the RTL model. SOLUTION: The interface model 102 wherein a necessary number of delay elements (108, 109) according to an input/output protocol are interposed between respective signal lines is configured so as to adjust timing of signal propagation to the operation model 403 from the RTL model 101, and the RTL model 101 and the operation model 103 are interconnected by the interface model 102. Thereby, a controller is eliminated. By holding only necessary data, the memory size is optimized. Thereby, high precision and high speed of the simulation are realized. COPYRIGHT: (C)2004,JPO
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