发明名称 PULSE DELAY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a pulse delay circuit having precise and wide-ranging adjustable delay time. SOLUTION: This pulse delay circuit has a counter which operates an input signal as a trigger, a frequency variable means for varying the frequency of a clock signal which the counter concerned counts, and a pulse generating means to form a delayed pulse, in response to output of specified number from the counter. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004153722(A) 申请公布日期 2004.05.27
申请号 JP20020318943 申请日期 2002.10.31
申请人 SANYO ELECTRIC CO LTD 发明人 UNO JUICHI
分类号 H03K5/135;(IPC1-7):H03K5/135 主分类号 H03K5/135
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