| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generating circuit for suppressing variations of a generated clock by controlling an oscillating frequency of a VCO within a prescribed range when a frequency fluctuation of an input reference clock is great. <P>SOLUTION: A reference clock adjustment circuit 10 compares a phase of a feedback clock subjected to 1/M frequency division with the input reference clock so that the phase of the clock generated by a VCO 50 is the same as the phase of the input reference clock. Then as a result of comparison, when the phase of the input reference clock is led or lagged by a prescribed range or over, an adjusted reference clock resulting from adjusting the input reference clock is outputted to a phase comparator 20. <P>COPYRIGHT: (C)2004,JPO |
