DDR component esp. DDR-DRAM for clocked coordination and commutation of data, comprises first and second clock-pulse relaying devices for differential and single-ended clock signals

摘要

A component, especially a DDR-semiconductor component i.e. a DDR-semiconductor memory component, has differential input-clock pulses (CLK, CLKt;/CLK,/CLKt) applied to the terminals. The component has in addition a first and second clock-pulse relaying device, in which the first device (51) is provided for relaying the differential input signals and the second device (50) for relaying a single-input (single-ended) clock-signal (CLK,CLKt).