发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS TEST METHOD
摘要 PURPOSE: To perform a scan test without lowering security. CONSTITUTION: This circuit is constituted so that a flip-flop constituting a scan chain is reset when the scan test is started or finished by an edge of a mode signal for switching between an ordinary operation and the scan test. An internal storage means can not be accessed at the scan test time. A dummy flip-flop operating only at the scan test time is connected to the scan chain, and shift-out by the scan chain can not be performed at the ordinary operation time.
申请公布号 KR20040026597(A) 申请公布日期 2004.03.31
申请号 KR20030057606 申请日期 2003.08.20
申请人 SONY CORPORATION 发明人 KAYUKAWA YOSHITAKA;AOKI TETSUYA;HAMAGUCHI TAKAHIRO;OSHIMA NORIYUKI
分类号 G01R31/28;G01R31/317;G01R31/3185;G06F11/22;H01L21/66;(IPC1-7):G01R31/28 主分类号 G01R31/28
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