发明名称 Linearized digital phase-locked loop
摘要 A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second value indicates a position of a second edge of the data signal and (D) adjusting the clock signal, based on the result of step (C), if the result is greater than a predetermined value.
申请公布号 US6711226(B1) 申请公布日期 2004.03.23
申请号 US20000747262 申请日期 2000.12.22
申请人 CYPRESS SEMICONDUCTOR CORP. 发明人 WILLIAMS BERTRAND J.;DALMIA KAMAL;LITTLE TERRY D.
分类号 H03L7/081;H03L7/085;H03L7/091;H04L7/033;(IPC1-7):H04L25/36;H04L7/00;H04L25/40 主分类号 H03L7/081
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