发明名称 |
Method and circuit for accelerating redundant address matching |
摘要 |
There is provided a latched comparison circuit for generating complementary latched output signals. The latched comparison circuit includes a comparator circuit for comparing an input address with a redundant address for generating a comparison output signal. The latched comparison circuit further includes a flip-flop circuit coupled to the comparison output signal for latching the comparison output signal and for providing complementary latched comparison output signals in response to a clock signal.
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申请公布号 |
US6707734(B2) |
申请公布日期 |
2004.03.16 |
申请号 |
US20030336849 |
申请日期 |
2003.01.06 |
申请人 |
MOSAID TECHNOLOGIES INCORPORATED |
发明人 |
DEMONE PAUL |
分类号 |
G11C7/00;G11C29/00;H03K3/037;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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