| 摘要 |
A frequency comparator detects the phase of a data signal DATA by using four-phase clocks ICLK, /ICLK, QCLK and /QCLK as a reference and detects a change in the phase. A counting processing unit counts a period in which a control signal UP2 or DN2 is activated within a predetermined period, and outputs an overflow detection signal LOL2 if the frequency is high. A hysteresis generating unit changes a signal LOL to the L level only after signal LOL goes low X times consecutively. On the other hand, after signal LOL is set to the L level once, the hysteresis generating unit changes signal LOL to the H level only after signal LOL2 goes high X times consecutively. With such a configuration, a phase-locked state detecting circuit with reduced malfunction even when a data signal having larger jitter is input can be provided.
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