发明名称 System for delaying the counting of occurrences of a plurality of events occurring in a processor until the disposition of the event has been determined
摘要 A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.
申请公布号 US6701447(B1) 申请公布日期 2004.03.02
申请号 US20000656547 申请日期 2000.09.06
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BASS BRIAN MITCHELL;DAVIS GORDON TAYLOR;HEDDES MARCO C.
分类号 G06F1/04;G06F11/34;H04L12/56;(IPC1-7):G06F1/04 主分类号 G06F1/04
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