| 摘要 |
Logic verification is performed based on correspondence information and compile information. The correspondence information specifies information on pairs of fragments of descriptions to be compared for equivalence in a behavioral level description written in a programming language and an RT level description obtained through behavioral synthesis and information on pairs of signals to be compared for each of the description pairs. The compile information includes mapping information between the behavioral level description and an object code. A logic cone extraction section extracts first logic cones from the object code through symbolic simulation by referencing the correspondence information and the compile information. The logic cone extraction section extracts second logic cones from the RT level description. A logic cone comparison section verifies equivalence between the first and second logic cones.
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