| 摘要 |
PROBLEM TO BE SOLVED: To perform a plurality of data bus processings by a serial bus processing by time division multiplex, and to obtain a data bus processing circuit compressed the scale of a processing circuit. SOLUTION: This data bus processing circuit is provided with a timing circuit A22-A which generates a processing timing signal 28-A identifying data to be processed among multiplexed signal 26-A generated by a multiplex circuit 21, a processing circuit 24-A which inputs the multiplexed signal 26-A and performs a prescribed processing based on the processing timing signal 28-A, and a separation circuit 25 which separates the multiplexed signal 26-C processed by the processing circuit 24-A into each data. COPYRIGHT: (C)2004,JPO
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