发明名称 |
Method for functional verification of an integrated circuit model for building a verification platform, emulator equipment and verification platform |
摘要 |
<p>In a first stage an autonomous emulator (1) is set up which replaces a low level language integrated circuit (IC) model by a high level language model able to perfect an environment emulator (51) from bus (30) data. The emulator (1) includes a calculator (10), memory (2) containing high level specification response data (20) and program memory (9). The second stage checks the IC program model against the emulator (1) : An independent claim is also included for : A verification platform which enables customers to check outputs against inputs on special purpose ICs using a functional specification.</p> |
申请公布号 |
EP1387304(A1) |
申请公布日期 |
2004.02.04 |
申请号 |
EP20030291871 |
申请日期 |
2003.07.29 |
申请人 |
BULL S.A. |
发明人 |
KASZYNSKI, ANNE;ABILY, JACQUES |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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