METHOD FOR FABRICATING MOS TRANSISTOR

摘要

PURPOSE: A method for fabricating a MOS transistor is provided to reduce the junction capacitance and the gate delay and enhance the reliability by preventing the increase of the well doping density of a source/drain region. CONSTITUTION: A buffer oxide layer is formed on a semiconductor substrate(21) including an isolation layer(23). An ion implantation process is performed. The buffer oxide layer is removed. A trench is formed by patterning a sacrificial layer. A gate oxide layer(31a) is formed on the semiconductor substrate(21) of a bottom of the trench. A polysilicon layer(31b) is formed on the sacrificial layer. A gate electrode(31) is formed by patterning the polysilicon layer(31b). The sacrificial layer is removed. An LDD region(33) is formed on the semiconductor substrate of both sides of the gate electrode(31). A spacer(37) is formed on both sidewalls of the gate electrode. A source/drain region(35) is formed on the semiconductor substrate of both sides of the gate electrode.