| 摘要 |
The figure shows a unit (5) for distributing clock signals (SA1, SB1) in telecommunication systems. The unit is provided with a semiconductor arrangement (ADA, CTA, RDA) for generating a predetermined time delay. Two clocks (CLA, CLB) are connected to two parallel, redundant semi-conductor or circuits (SCA, SCB) emitting clock signals (SA2, SB2) from multiplexers (MXA, MXB). These receive delayed clock signals (SA1) from one of the clocks (CLA), and from the other clock (CLB) clock signals (SB1) that are delayed in adjustable delay circuits (ADA, ADB) to be phased in with the clock signals (SA1) from the first clock Thus, a number of delay elements in the delay circuit (ADA) are connected and a first reference number of delay elements, providing a predetermined delay time, are connected in a reference delay circuit (RDA). A quotient of the two numbers is stored. One of the semi-conductor circuits (SCA) is replaced by an alternative semi-conductor circuit (SCA1), the reference delay circuit (RDA1) of which is set on the predetermined delay time, corresponding to a second reference number of delay elements. An adjustable delay circuit (ADA1) is set on the same delay time as the replaced semi-conductor circuit (SCA, ADA), by means of the second reference number and the quotient. The adjustable delay circuit (ADA, ADA1) and the reference delay circuit (RDA, RDA1) on the same semi-conductor circuit (SCA, SCA1) must be produced in a common process to enable all the delay elements to have identical time delays.
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