| 摘要 |
PURPOSE: A multi chip system having a continuous burst read mode is provided to enable a read operation continuously from the first address of the second chip without latency when an address reaches the end of the first chip during a burst read operation. CONSTITUTION: According to a synchronous semiconductor memory device having a burst read operation mode comprising a plurality of internal burst cycles, a memory cell array(200) stores data information. An address generation circuit(220) operates by being synchronized to a clock signal and generates internal addresses for the burst read operation sequentially in response to an external address. Data read circuits(230,240,260) read burst data to be output during each internal burst cycle from the memory cell array according to a part of the internal address. Read control circuits(210,250) control the read operation of the data read circuits during transition of the external address or the internal address, and operate in response to a read enable signal. A burst control circuit(300) generates a latch enable signal synchronized to a clock signal, and operates in response to a burst enable signal. Data registers(310,320) latch the burst data read by the read circuit in response to the latch enable signal, and output the latched burst data sequentially in response to the remaining of the internal address. And a detector detects whether the internal address reaches a burst address set corresponding to the last internal burst cycle among the internal burst cycles, and generates the burst enable signal and the read enable signal to control the burst control circuit and the read control circuit according to the detection result.
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