发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To operate an SRAM (static random access memory) circuit at a state that an operation margin is reduced, particularly in a low power source voltage state by increasing or optimizing the operation margin of the SRAM circuit. <P>SOLUTION: In the SRAM circuit, a power source voltage of a memory cell is adjusted, an optimal voltage is compared with a power source voltage of an auxiliary circuit by detecting a threshold voltage of a manufactured transistor, and substrate bias is further controlled. <P>COPYRIGHT: (C)2004,JPO</p>
申请公布号 JP2004005777(A) 申请公布日期 2004.01.08
申请号 JP20020156646 申请日期 2002.05.30
申请人 HITACHI LTD 发明人 YAMAOKA MASANAO;OSADA KENICHI
分类号 G11C11/413;G11C11/417;G11C11/419;G11C11/4193;G11C29/02;(IPC1-7):G11C11/413 主分类号 G11C11/413
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