发明名称 Digital-signal receiving apparatus
摘要 A plurality of data items are received in each frame period. A digital signal processor (DSP) checks the flag corresponding to each data item in each frame period before the DSP applies processing to the received data. When the checked flag allows the corresponding data item to be processed, the process is performed. When the execution of the process is finished, the flag is reset. When all the flags are reset, the DSP enters a sleep state. Typical application is within the EUREKA 147 system. <IMAGE>
申请公布号 EP1148652(A3) 申请公布日期 2004.01.02
申请号 EP20010303476 申请日期 2001.04.12
申请人 SONY CORPORATION 发明人 FUKAMI, TADASHI
分类号 H04N5/44;H04B1/16;H04J11/00 主分类号 H04N5/44
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