发明名称 |
Semiconductor memory device and test method thereof using row compression test mode |
摘要 |
A circuit and method for testing a semiconductor memory device using a row compression test mode is provided. The testing circuit includes at least one equalizer circuit for supplying a first voltage level to one of at least one true bitline or at least one complement bitline during a test mode; an equalizing line for coupling a plurality of equalizer circuits along a wordline; and a comparator for comparing a second voltage on the equalizing line during the test mode to a reference voltage, wherein if the second voltage is less than the reference voltage, the wordline is defective.
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申请公布号 |
US6667919(B1) |
申请公布日期 |
2003.12.23 |
申请号 |
US20020256181 |
申请日期 |
2002.09.26 |
申请人 |
INFINEON TECHNOLOGIES, AG |
发明人 |
MA DAVID SUITWAI;BRUCKE PAUL EDWARD;HOEHLER RAINER |
分类号 |
G11C29/40;(IPC1-7):G11C7/00 |
主分类号 |
G11C29/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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